基于FPGA的部分并行QC-LDPC译码器高效存储方法

Efficient storage method for FPGA-based partially parallel QC-LDPC decoder

针对部分并行结构的准循环低密度校验(QC-LDPC)码译码器,提出了一种将译码准码字存储在信道信息和外信息存储块中的高效存储方法,该方法不需要额外的存储块来存储译码准码字,能够减少译码器实验所需的存储资源数量,并且有效降低了译码电路的布线复杂度。在Xilinx XC2V6 000-5ff1 152 FPGA上的实验结果表明,提出的QC-LDPC码译码器设计方法能够在降低系统的BRAM资源需求量的同时有效地提高系统的运行频率和译码吞吐量。

An efficient storage method of hard decisions sharing intrinsic and extrinsic memory banks for partially parallel QC-LDPC decoder was proposed. Extra memory banks for storing hard decisions were avoided in this method, which result in significantly reduced consumption of RAM resources and routed complexity. Implementation results based on a Xilinx XC2V6 000-5ffl 152 FPGA show that the proposed method improves the frequency and decodes throughput of the system, and significantly reduced the requirements for the number of BRAM.