SRAM型FPGA带刷的新分层三模冗余技术容错分析

Single-event upsets fault-tolerant method for SRAM-based FPGA

SRAM型FPGA(field programmable gate array)因为其具有信息密度大、性能高、开发成本低、可重复编程等特性,受到航天电子方面设计者青睐,越来越多地被应用于需要高可靠性的复杂空间环境。然而,相比于传统的ASIC电路设计,由于FPGA对辐射的潜在敏感性,易引发单粒子翻转效应(single-event up-sets,SEUs),甚至可能造成系统失效。该文提出一种全新的三模冗余技术(triple modular redundancy,TMR)来削弱空间粒子对FPGA的影响,这项技术可以减轻FPGA中采用映射设计的配置位受到SEUs的影响。通过逐位翻转故障注入实验验证显示,相对于传统的TMR设计,采用该新技术防护的FPGA中易收到SEUs影响的配置位减少了87%。

SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, compared to ASIC designs, the technology of SRAM-based FPGAs is very sensitive to single-event upsets （SEUs） and particular concerns arise from SEUs affecting the FP- GAs＇ configuration memory. This paper proposes a new TMR method for mitigating the impact of faults on the FPGA dependability. This technique is able to tolerate SEUs in configuration bits of mapped designs. The effectiveness of the new technique is demonstrated by a bit-by-bit upset fault injection experiment showing that the sensitive bits might cause SEU effects in the FPGA＇s configuration memory decreasing 87% with respect to a standard TMR design technique.