基于CORDIC算法的流水线型FFT处理器设计

Design of Pipeline FFT Processor Based on CORDIC

首先分析了基二FFT算法的原理以及在FPGA上实现FFT处理器的硬件结构。其次详细研究了在FPGA上实现FFT的具体过程,利用CORDIC算法实现了旋转因子乘法器,解决了整体设计过程中主要面对的几个关键问题,最终利用Verilog编程实现了基二流水线型FFT处理器,利用MATLAB与MODELSIM结合仿真结果表明该设计满足FFT处理器的基本要求,在10 MHz的采样率下完成32点FFT只需要14.45μs,设计方法也简单易行,具有一定的推广价值。

Firstly, the radix-2 FFT theory and hardware structure on FPGA is analyzed. Next, detailed FFT realization process on FPGA is studied, twiddle factor multiplier is realized by using CORDIC, several crucial questions in the implementation is solved. At last, the pipeline FFT processor is re- alized by using verilog hardware description language. The simulation resuls by using MODELSIM and MATLAB show that the design basically meets the requirements. In 10 MHz sample rate, 32-point FFT need only14.45 μs, the method is very simple and worth popularization.