基于FPGA并行处理SIFT算法特征点检测

Realization of SIFT Feature Detection Parallel Implementation Based on FPGA

由于SIFT算法计算量大,以至于不能够应用于实时性要求高的领域。为了使SIFT算法满足实时性的需求,详细阐述了SIFT算法中特征点检测与梯度计算硬件实现过程和系统架构,并且对SIFT算法进行相应的改进,使其适合FPGA并行处理特性。最后利用Altera公司Cyclone III系列芯片的硬件平台测试SIFT算法硬件部分的计算时间和匹配性能,并且与DSP实现的SIFT算法进行性能上的比较。结果表明,FPGA实现SIFT算法具有实时性高,匹配性能好的特点。

Due to large calculated amount of SIFT algorithm, it is not used in real-time field. In order to the real-time demand for SIFT algorithm. Hardware realization and system architecture that characteristic points detection and calculating pixel＇ s gradient calculation in SIFT algorithm are realized by FPGA is introduced in this paper. And SIFT algorithm is optimized for the parallel processing characteristic of FPGA. Calculating time and matching performance can be test by FPGA IC chip of the Altera Cyclone III series and matching performance can be compared SIFT in FPGA with SIFT in DSP. Finally, FPGA implementation of SIFT algorithm have characteristic of high real-time and matching performance.