基于同步参考坐标系的三相数字锁相环

Three-Phase Digital Phase-Locked Loop Based on Synchronous Reference Frame

基于同步参考坐标系的三相数字锁相环的动态性能取决于比例积分环节的参数设计、角频率静态偏置补偿误差及相位静态偏置补偿误差,本文通过构造李雅普诺夫函数验证了三相数字锁相环的非线性模型全局渐进稳定性,保证基于线性模型设计的PI参数的有效性;提出了基于过零检测的电网三相电压相序识别方法以保证角频率静态偏置的正确补偿,推导出了该方法下综合抗干扰能力最强的过零检测滞环幅值的求解公式,将相序识别时获得的初始相位用于锁相环的相位静态偏置补偿,使锁相环的调整时间缩短到过零点的等待时间及滞环电压引起的过零点误差调整时间。最后,仿真和实验证明了该方法的可行性。

The dynamic performance of three-phase digital phase-locked loop （PLL） based on synchronous reference frame depends on the proportional and integral （PI） parameters, compensation errors of angular frequency and phase angle static bias. The nonlinear model of the PLL is proved to be globally asymptotically stable with the design of Lyapunov function, which assures the validity of the PI parameters designed on the linear model. A grid phase sequence identification method based on zero-crossing detection is presented to guarantee the correct compensation of the angular frequency static bias. And the hysteresis voltage for zero-crossing detection is deduced to obtain the largest anti-interference margin. The initial phase angle is identified during phase sequence identification, and it could be used to compensate the phase angle static bias. Then the set-up time of the PLL could be greatly shortened to the waiting time of the zero-crossing and the set-up time of zero-crossing error due to the hysteresis voltage. Finally, the advantages mentioned above are verified by simulations and experiments.