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智能模数控制型全数字锁相环的研究 被引量:1

The research on all digital phase-locked loop of intelligent module control type
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摘要 由K模可逆计数器构成的传统数字锁相环可简单实现,但存在缩短捕获时间与减小同步误差之间的矛盾,而且获得的频带宽度较窄,因此设计了一种智能模数控制型全数字锁相环.其能够根据环路工作的不同阶段自动调整K值的大小,进而缩短捕获时间和减小同步误差.采用一个特殊的鉴频锁存器控制分频器的系数,能够调整环路的中心频率和扩宽频带宽度. The realization of the traditional digital and phase-locked loop which consists of K reversible counter is simple, but there is a contradiction between shortening the time of capture and the synchronization error, and the bandwidth of the loop is narrower. Therefore, authors designed the digital phase-locked loop of intelligent module control, which could work according to the different stages of loop automatically and adjust the size of the K value. It could shorten the time of the capture and reduce the synchronization error. Since the coefficient of frequency divider was controlled by a special frequency discriminator latched, the center frequency loop was adjusted and the frequency bandwidth was broadened.
出处 《安徽大学学报(自然科学版)》 CAS 北大核心 2012年第6期51-56,共6页 Journal of Anhui University(Natural Science Edition)
基金 863计划资助项目(2009AA012201) 专用集成电路与系统国家重点实验室开放基金资助项目(10KF014) 安徽大学全日制研究生学术创新研究强化基金资助项目
关键词 全数字锁相环 智能模数控制器 鉴频锁存器 VERILOG HDL all digital phase locked loop intelligent modulus control frequency discriminator latch Verilog HDL
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  • 1胡春华 石玉.数字锁相环路原理与应用[M].上海:上海科学技术出版社,1990..
  • 2BEST R E. Phaselocked loops design,simulation,and applica.tions [M]. 5th ed.北京:清华大学出版社,2007.
  • 3ZIANBETOV E,JAVIDAN M,ANCEAU F,et al. Design andVHDL modeling of all.digital PLLS [C]// NEWCAS Conference,New York,USA:IEEE,2010:293-296.
  • 4GENG Hua,XU De.wei,WU Bin. A novel hardware.based all.digital phase.locked loop applied to grid. connected power con.verters [J]. IEEE Transactions on Industrial Electronics,2011,58(5):1737-1745.
  • 5YAHARAL M,SASAKI H,FUJIMOTO K,et al. All digital di.viding ratio changeable type phase.locked loop with a wide lock.in range [J]. Electronics and Communications in Japan(Part1:Communications),2005,88(2):2277-2284.
  • 6CHENG Kuo.hsing,LIU Jen.chieh,HUANG Hong.yi. A 0.6 V800 MHz all.digital phase.locked loop with a digital supplyregulator [J]. IEEE Transactions on circuits and systems,2012,59(12):111-119.
  • 7许春香,时伟,黄传金,陈良,甄敬然.基于FPGA的高精度时间数字转换电路设计[J].微计算机信息,2009,25(2):208-210. 被引量:5
  • 8肖帅,孙建波,耿华,吴舰.基于FPGA实现的可变模全数字锁相环[J].电工技术学报,2012,27(4):153-158. 被引量:34

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