摘要
针对直接数字频率合成器(DDS)电路系统输出杂散问题,分析DAC非线性对输出杂散的影响,在此基础上给出DDS电路系统杂散的来源模型。提出通过合理选择输出频段来减小DDS输出杂散的方案,并给出了仿真实例。实测结果验证了该方案可以有效地降低DDS输出杂散,对提高DDS电路输出信号的质量有很好的促进作用,在DDS电路设计方面具有指导意义。
In order to suppress the output spurious of the direct digital frequency synthesizer （DDS） circuit, the authors analyzed the effect of DAC nonlinear on the output spurious, and on the basis, gave a spurious source model for DDS circuit. A program was proposed to choose a reasonable output frequency band orderly to reduce the DDS output spurious, and the simulation instances were given. The experimental results indicated this program could effectively reduce the DDS output spurious, and played a good role in improving the quality of the output signal of the DDS circuit. It was an important guiding significance in the DDS circuit design.
出处
《中国测试》
CAS
北大核心
2012年第6期71-74,100,共5页
China Measurement & Test
基金
国家自然科学基金青年基金(51107147)
