基于E1接口的时间同步系统关键模块设计与仿真

Design and simulation of key modules of time synchronous system based on E1 interface

针对E1线路延迟稳定的优点,给出了溯源到GPS系统时间的时间保持模块,提出时间信息组合以适应E1线路不成帧的传输方式,采用HDB3码作为E1线路传输码型,利用FPGA芯片EP2C8T144I8进行开发,设计了基于E1接口的时间同步系统关键模块,并对各关键模块进行仿真,结果表明各模块设计均满足时间同步系统的要求。

According to the advantage of the stable transfer delay of E 1 interface, the time keeping module which can trace to the time of GPS System is proposed. The time information combination is given in order to adapt to the no framed transfer method for E1 interface. By using the HDB3 code as the transmission code and adopting the EP2C8T14418 FPGA chip, the key time synchronous system module of E1 interface is designed. The simulations of the key modules are conducted and the results indicate that all the key modules meet the requirements of the time synchronization system.