多核处理器结构与核间通信的CMC总线设计

The CMC Bus Design of Inter-core Communication in the Multi-core Processor

CMC(Core Memory Core)总线是为多核处理器或众核处理器的内部通信设计的一种高效解决方案。目前多核处理器以其性能优势取代了单核处理器,多核处理器的体系结构仍有很多的关键技术亟待解决,包括核间通信问题。讨论了目前多核处理器中使用的核间通讯技术,分析了优缺点,在此基础上提出了CMC总线。CMC总线的设计目标为只需一根握手信号线,简单的硬件逻辑,并为软件提供必要的控制接口。最后利用Modelsim SE仿真软件对CMC总线的读写进行仿真,验证了该总线作为一种高效的多核处理器核间通信方案的可行性。

he CMC （CoreMemoryCore）bus provides an efficient solution for the inter core communication in the multicore processor or manycore processor. The singlecore processor has been replaced by the multicore processor with its advantages. There are many key technologies in the architecture of multicore processor to be solved, including the inter core communication. This article discusses some advantages and disadvantages of current intercore communication technologies in the multicore processor, so we design the CMC bus. Our design goals of the CMC bus are just to achieve a handshake signal, simple hard ware logic and enough software interfaces. Finally simulating reading and writing of the CMC bus with Modelsim SE is used to verify the feasibility of CMC bus as a solution to the intercore communication.