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Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array
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摘要 A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies. A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies,
出处 《Journal of Central South University》 SCIE EI CAS 2012年第12期3484-3491,共8页 中南大学学报(英文版)
基金 Project supported by the Second Stage of Brain Korea 21 Projects supported by Industrial Strategic Technology Development Program funded by the Ministry of Knowledge Economy (MKE,Korea)(10039239,"Development of Power Management System SoC Supporting Multi-Battery-Cells and Multi-Energy-Sources for Smart Phones and Smart Devices")
关键词 eFuse one-time programmable memory 2-dimensional array OTP存储器 设计变量 32位 差分 阵列 读出放大器 存储单元 二维数组
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