面向RMAP协议的SpaceWire节点IP核设计

Design of SpaceWire IP Core for RMAP

在对SpaceWire传输层协议——远程存储器访问协议进行研究分析的基础上,采用Verilog HDL硬件描述语言,设计了一种符合RMAP协议规范的IP软核;可配置实现RMAP事务发起和事务响应功能,经功能仿真和FPGA原型验证测试,结果表明IP核符合标准规范,支持协议规定的所有指令类型,具备良好的通用性、可扩展性并可灵活配置,可实现与其它传输层协议的兼容以及和更高层协议的无缝衔接。

Based on research of SpaceWire＇s transport layer protocol （remote memory access protocol, RMAP）, a RMAP--compliant SpaceWire node IP core is designed with hardware description language Verilog HDL, in which RMAP transaction initiator and target responder can be configured. The results of function simulation and FPGA prototyping verification show that the IP core which supports all of the instructions in RMAP agreement, has good universality, high scalability and configurability. Moreover, the IP core is compatible with other transport--layer protocols and can be easily connected to the higher layer protocols.