适用于D类音频功放的PWM高速比较器设计

Design of High-Speed PWM Comparator for Class D Audio Power Amplifier

设计了一种应用于CMOS D类音频功率放大器的PWM高速比较器。输入级为Rail-to-Rail结构,中间级由锁存器和自偏置差分放大器组成,输出级为反相器结构。由于采用了锁存器和自偏置放大器结构,比较器可以在很短的时间内驱动大电容,满足后续电路对驱动能力的要求。基于CSMC 0.5μm CMOS工艺的BSIM3V3Spice模型,采用Hspice对PWM比较器进行仿真。结果表明,在典型模型下,比较器的电源抑制比为56dB,直流开环增益为45dB,输入共模范围(ICMR)为-0.19～4.93V,传输延时为15ns。

A high-speed comparator for PWM CMOS Class D audio power amplifiers was designed. In the comparator, a rail-to-rail structure was adopted for input stage, and the intermediate stage was composed of a latch and a self-biased differential amplifier, while an inverter was used as output stage. Because of its latch and self- biased amplifier structure, the comparator could drive large capacitive load in a very short time, satisfying the requirement of the subsequent circuit for driving capability. Based on BSIM3V3 Spice model of CSMC＇ s 0. 5 ~m CMOS process, the comparator was simulated using Hspice. Results showed that, under the typical model, the circuit had a PSRR of 56 dB, a DC openqoop gain of 45 dB, an ICMR from -0.19 V to 4.93 V, and a transmission