采用RDF的硅物理不可克隆函数设计与评估

Design and Evaluation of Silicon Physical Unclonable Functions Using Random Dopant Fluctuation Model

利用65nm CMOS制造工艺下的随机掺杂涨落(RDF)模型,建立起随机路径延时模型,通过修改台积电(TSMC)65nm低k电介质工艺器件模型库参数,完成了仲裁器型PUF电路的设计和评估。实验在Synopsys Hspice C-2010模拟设计平台上完成,测量了PUF电路的片间差异和片内差异参数,评估了128位PUF电路的性能。与实测电路参数的对比结果证明了该方法的有效性。

A random path delay model was established by using random dopant fluctuation （RDF） model for 65 nm CMOS process technology. Parameters of TSMC^s 65 nm logic salicide [ow-k IMI） Spice model were modified to simulate arbiter PUF circuits with delay model embedded. Experiments were conducted on Synopsys Hspice C-2010 analog design platform, on which both inter-chip and intra-chip variations of PUF circuit were measured to evaluate the performance of a 128-bit PUF circuit. Measured parameters were compared with real PUF circuit to demonstrate the effectiveness of the method.