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一种用于高速流水线ADC的数字延迟锁相环电路 被引量：1

A Digital Delay Locked Loop for High-Speed Pipelined A/D Converter
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摘要 给出了一种应用于高速流水线A/D转换器的数字延迟锁相环电路。该电路的锁定过程采用顺序查找算法,设计了锁定检测窗口,用来判断延迟后的输出时钟信号是否满足锁定条件,根据检测结果即时调整延时大小,能有效避免误锁现象,准确完成延迟锁相功能。该数字延迟锁相环采用SMIC 0.18μm 1.8VCMOS工艺实现,频率范围为40～250MHz。在输入最大频率下,仿真的锁定时间约为690ns,抖动约为1.5ps。 A digital delay locked loop （DLL） for high-speed pipelined ADC was designed. Sequential search algorithm was used in the locking process. The DLL decided if the delayed output signal met locking conditions by locking detect window. The delay size was adjusted according to the detection, to avoid false locking. Implemented in SMIC＇s 0. 18 μm 1.8 V CMOS process, the digital DLL could operate from 40 MHz to 250 MHz. At maximum input frequency, the synthesizer had a locking time of about 690 ns and a jitter of about 1.5 ps.
作者 周洁 陈珍海 于宗光
机构地区 江南大学物联网工程学院 中国电子科技集团公司第五十八研究所
出处 《微电子学》 CAS CSCD 北大核心 2012年第6期827-831,共5页 Microelectronics
基金 江苏省333工程科研项目资助(BRA2011115)
关键词 数字延迟锁相环 检测窗口 顺序查找算法 低抖动 Digital delay locked loop Detect window Sequential search algorithm Low jitter
分类号 TN432 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献10

  • 1马聪,蒋颖丹,田应洪,许帅,石艳玲,赖宗声.一种用于流水线ADC的可调节多相时钟产生电路[J].微电子学,2010,40(5):640-643. 被引量：1
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二级参考文献5

  • 1陈丹凤,陆平,李联,任俊彦.适用于HDTV的低抖动时钟电路[J].微电子学,2007,37(1):147-150. 被引量：2
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同被引文献6

  • 1LEEMJ E, DALLYWJ, GREERT, et al. Jitter transfer characteristics of delay-locked loops - theories and design techniques [J]. IEEE J Sol Sta Cite, 2003, 38(4) : 614-621.
  • 2SONG E, LEE S-W, LEE J-W, et al. A reset-free anti-harmonic delay-locked loop using a cycle period detector [J]. IEEE J Sol Sta Circ, 2004, 39 (11) 2055-2061.
  • 3GAO W, GAO D, BRASSE D, et al. Precise multiphase clock generation using low-jitter delay-locked loop techniques for positron emission tomography imaging [J]. IEEE Trans Nuclr Sci, 2010, 57(3) : 1063-1070.
  • 4FAHIMAM.时钟发生器在片上系统处理器中的应用[M].北京:科学出版社,2007.
  • 5CHOI J, KIM S-T, KIM W, et al. A low power andwide range programmable clock generator with a high multiplication factor [J]. IEEE Trans VLSI, 2011, 19 (4) : 701-705.
  • 6KUO C-H, LAI H-J, LIN M-F. A multi-band fast- locking delay-locked loop with jitter-bounded feature [J]. IEEE Trans UFFC, 2011, 58(1): 51-59.

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二级引证文献3

微电子学
2012年 第6期

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