超高速数字分幅相机中快门控制电路设计

Design of a Shutter Control Ciruit for High-Speed Digital Framing Camera

超高速数字分幅相机作为一种利用光学系统静态分幅、快门控制电路系统控制摄影的高速相机,具有良好的空间分辨率,时间分辨率高达ns级,提出了一种可获得超高速数字分幅相机所需的高速快门控制电路的设计方案;利用高速CPLD控制模拟延时线(Delay Line)芯片进行精确延时,得到脉冲宽度可调、时间分辨率极高(0.25ns)的低压脉冲,利用单片机实现PC端对电路延时参数的设定。

High-speed digital framing camera as a use of optical system of static amplitude,the shutter control circuit system to control of the high speed photography camera,has good spatial resolution,time high resolution to nano seconds level.This paper puts forward a high-speed digital points of the high speed camera shutter control circuit of design project.Using high-speed CPLD control simulation Delay Line chips for accurate delay,pulse width of the two volatage（pressure）pulse can be adjusted,its time high resolution reaches 0.25 ns.And a single chip microcomputer can be used to set up circuit paraments for PC.