S波段低相噪捷变频频率综合器设计

Design of a S-band, Low Phase Noise and Frequency Agility Frequency Synthesizer

介绍了一种S波段低相噪捷变频频率综合器设计方法。由于采用DDS+PLL的方式使此频率综合器相噪优于-115dBc/Hz@1kHz,跳频时间小于5us。

The design of a S-band frequency synthesizer with low noise and frequency agility is introduced. For the synthesizer attributed to the use of DDS＋PLL, the phase noise is superior to -115dBc/Hz@lkHz and frequency change time is under 5us.