基于边界扫描的S-P低功耗测试结构设计

Design of S-P low test power structure based on boundary scan

边界扫描技术的提出给集成电路的测试带来极大方便,但集成电路随着半导体技术的发展变得越来越复杂,导致测试功耗迅速提高,对芯片造成一定甚至不可挽回的影响。为降低测试功耗,本文深入研究边界扫描原理,通过理论分析及计算,提出了串并转换(serial-parallel conversion,S-P)测试结构,在保证故障覆盖率的前提下有效的减少了位通过率RBP(rate of bite propagation),与传统结构相比该测试结构可使位通过率降低90%以上,从而有效的降低了测试功耗中的动态功耗。关键词:边界扫描;测试结构;位通过率;低功耗;

By proposing boundary scan technology,great convenience will be brought in the integrated circuit test.But with the development of the semiconductor technology,integrated circuit becomes more and more complex,leading to a rapid increase in test power which may cause certain or even unavoidable impact on the chip.This paper researches deeply the boundary scan principle,proposes serial-parallel conversion （S-P） test structure by means of theoretical analysis and calculation.On the premise of ensuring fault coverage,this test structure can reduce RBP（rate of bite propagation） more than 90% compared with traditional structure,thus,effectively lower the dynamic power in test power.