低功耗四边沿触发器设计

Design of low power quad-edge-triggered flip-flop

根据在保持电路原有性能的前提下可通过降低时钟频率来降低系统功耗的原理和双边沿触发器的设计思想,本文将多值信号信息量大的优点应用于时钟网络上设计了基于三值时钟的四边沿触发器,消除了三值时钟的冗余跳变,从而通过降低时钟频率的方式达到降低功耗的目的。本文设计的四边沿触发器电路结构简单,既可以用于二值时序电路中也可以用于多值时序电路中。模拟结果表明,本文设计的四边沿触发器具有正确的逻辑功能且能有效地降低系统功耗。

A design of QETFF （quad-edge-triggered flip-flop） based on ternary clock is proposed according to the principle that power optimization of a circuit can be obtained through reductions of the clock frequency under the constraint that its original performance does exist and the design method of the binary DETFF （double-edge-triggered flip-flop） based on binary clock. Multivalued signals possess the large information-carrying capacity, which are applied in clock network in order to reduce the power dissipation of system. QETFF makes use of all the four edges of ternary clock with a simple structure, lowering power consumption for no redundant edges. HSPICE simulations show that the designed QETFF performs ideal logic functionality with low power that can serve in binary sequential circuits and also in multivalued sequential circuits.