一种新的8B/10B编解码设计

New kind of 8B/10B encoding and decoding design

在分析8B/10B编解码规则和输入信号与对应数据间逻辑关系的基础上,提出了一种新的编解码和游程值计算方法,完成了编解码电路的可综合Verilog HDL语言设计,并在Quartus Ⅱ和ModelSim软件环境下实现了电路综合及仿真。仿真结果表明,该方法与现有8B/10B编解码方案相比,最大工作频率显著提高,资源占用相对较少且可靠性得到增强。

Based on the analysis of the rules of 8B/10B encoding and decoding and the logical relationship be- tween the input signals and the corresponding data,the new methods for encoding and decoding and to calcu- late the run length are put forward.The algorithm of encoding and decoding are completed with synthesizable Verilog HDL and the simulations were achieved in QuartuslI and ModelSim software environments.The sim- ulation results show that the proposed method has the performance of the improved maximum working fre- quency, the less consumption resource and the enhanced reliability.