基于FPGA的并行高速相位累加器的设计

The Design of High Speed Phase Accumulator Based on FPGA

介绍了FPGA中常用相位累加器的设计方案,分析了超前进位加法和流水线结构不适合应用于相位累加器的原因,提出了并行技术在高阶高速度相位累加器的设计方案,在Quartus II环境下完成该设计的功能验证和时序验证,并以250MHz为系统时钟,成功运行在EP2C5Q208为主器件的硬件平台。该DDS相位累加器具有高速、低资源消耗等优点,易于移植于FPGA中的查表式DDS。

The design methods of phase accumulator based on FPGA are introduced. The causes of the carry look-ahead adder and pipeline structure to be not applied to the phase accumulator are analyzed. The design scheme of the parallel technology in long width with high-speed phase accumulator is proposed. The design in function and scheduling is validated by the environment of QuartuslI. By using 250MHz as the system clock, it runs successfully in the EP2C5Q208 device hardware platform. The DDS phase accumulator has the advantages of high speed, low resources consumption, and easy to transplant to the FPGA of DDS.