基于FPGA的RS码译码器的设计

Design of RS decoder based on FPGA

介绍了符合CCSDS标准的RS(255,223)码译码器的硬件实现结构。译码器采用8位并行时域译码算法,主要包括了修正后的无逆BM迭代译码算法,钱搜索算法和Forney算法。采用了三级流水线结构实现,减小了译码器的时延,提高了译码的速率,使用了VHDL语言完成译码器的设计与实现。测试表明,该译码器性能优良,适用于高速通信。

The decoder structure of Reed-Solomon （255,223） according to CCSDS specification is introduced. It is given that some basic modules in finite field, the reformulated inversion less BM algorithm, and chien search algorithm and Foruey algorithm. The design is implemented with three pipelines which decrease the delay of decoder. The decoder is designed and implemented with YHDL. As test result shown, the performance of the decoder described in this paper is excellent and it is applied to high-speed communications.