摘要
提出了一种适用于AVS的高性能整像素运动估计的硬件设计。该设计采用了二维内置SAD加法树计算阵列结构,通过合理的安排片上存储,极大地降低了I/O带宽;运用了加1电路选择进位加法器,进一步缩小了结构面积,提高了处理速度。实验表明,使用SMIC 0.18μm CMOS工艺库在250 MHz频率下综合,所提出的结构只需102 K门,满足对AVS高清视频实时处理的要求。
In this paper, a high-performance hardware architecture proper for integer motion estimation in AVS is presented. In this architecture, we propose 2D SAD adder tree-PE matrix with the data storage caretidly organized to decrease I/0 bandwidth, and use the add-one carry select adder so as to reduce the area of architecture and improve the processing speed . The experi- ment shows the proposed design can achieve 250 MHz only with gate count of 102 K by using SMIC 0.18 μm CMOS technology, and this desizn satisfies the requirement of hizh definition video.
出处
《电子技术应用》
北大核心
2013年第1期40-42,46,共4页
Application of Electronic Technique
