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一种提高LDPC译码层内并行度的方法 被引量:2

An approach to improve parallelism inside layer in LDPC decoding
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摘要 普通准循环低密度校验码(QC-LDPC)按照SHIFT结构特性分层时,层内并行度难以提高。提出了一种非均匀抽取分层方法,可在保证层内行(列)重至多为1的前提下,提高层内并行度,并设计了相应的寻址结构和流水结构,进而提高吞吐率。对于实际应用中的2种标准码型——空间数据系统咨询委员会(CCSDS)深空通信(5 632,4 096)码和中国地面数字电视传输(DTMB)标准(7 493,6 096)码,层内并行度对比均匀抽取分别提升41.3%和32.2%。对深空通信码的综合结果表明,对比采用均匀抽取的译码器,使用双相消息传递译码算法时,可在相同资源利用率的情况下提高吞吐率41.3%;使用按列分层译码算法时,译码系统最大吞吐率可提升28.2%。 It is hard to increase parallelism inside layer when converting a generic Quasi Cyclic-Low Density Parity Check(QC-LDPC) code to a SHIFT-structured LDPC code.The paper proposes a non-uniform layered partitioning scheme,which can efficiently increase the parallelism inside layer while maximum row(column) weight of each layer is not more than one.Corresponding shuffle network and pipeline architecture are also designed.In contrast with uniform layered partitioning scheme,the proposed scheme can enhance the parallelism inside layer by 41.3% and 32.2% respectively for two application codes,Consultative Committee for Space Data Systems(CCSDS)(5 632,4 096) code and China Digital Television Terrestrial Multimedia Broadcasting(DTMB)(7 493,6 096) code.Synthesized results of(5 632,4 096) code show that the non-uniform scheme can improve the parallelism by 41.3% comparing to uniform scheme with the same resource utilization while using the Two Phase Message Passing(TPMP) algorithm;and the maximum throughput of the decoding system can be improved by 28.2% while using Shuffled Belief Propagation Decoding(SBP) algorithm.
出处 《信息与电子工程》 2012年第6期719-724,共6页 information and electronic engineering
关键词 准循环低密度校验码 高吞吐率 层内并行度 分层译码 译码器 Quasi Cyclic-Low Density Parity Check code high throughput parallelism inside layer layered decoding decoder
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参考文献18

  • 1Gallager R G. Low-density parity-check codes[J]. IRE Transactions of Information Theory, 1962,IT-8:21-28.
  • 2张昊,倪卫明.基于TCM的LDPC高效编码调制系统性能[J].信息与电子工程,2008,6(2):92-96. 被引量:3
  • 3冉欢欢,许渤.适合光纤通信的一种准循环LDPC编码器的实现[J].信息与电子工程,2008,6(6):429-432. 被引量:3
  • 4Chen Y ,Parhi K K. Overlapped message passing for quasi-cyclic low-density parity check codes[J]. IEEE Trans, onCircuits and Systems, 2004,51(6):1106-1113.
  • 5Blankshy A J,Howland C J. A 690-mW 1 -Gb/s 1024-b,rate-1/2 low-density parity check rode decoder[J]. IEEE Journal ofSolid-State Circuits, 2002,37(3):404-412.
  • 6Mansour M M,Shanhhag N R. Turbo decoder architectures for low-density parity-check codes[C]// Global TelecommunicationsConference. [S.l.]:IEEE Press, 2002,2:1383-1388.
  • 7Sharon E,Litsyn S,Goldberger J. An efficient message passing schedule for LDPC decoding[C|// Proc. 23rd IEEE Convention.Tel-A viv,Israel:[s.n.], 2004:223-226.
  • 8Hocevar D E. A reduced complexity decoder architecture via layered decoding of LDPC codes[C]// Proc. 2004 IEEE Workshopon Signal Processing Systems. Au8tin,TX,l)SA:[s.n.J, 2004:107-112.
  • 9Radosavljevic* P,Baynast A,Cavallaro J R. Optimized message passing schedules for LDPC DecodingfC]// 39th AsilomarConference on Signals,Systems and Computers. CA,USA:[s.n.], 2005:591-595.
  • 10ZHANG Juntan,MARC P C FOSSORIER. Shuffled Iterative Decoding[J]. IEEE Transactions on Communications, 2005,53(2):209-213.

二级参考文献20

  • 1陈朝,陈芳,周峰.一种基于MATLAB的Turbo码编码仿真实现[J].信息与电子工程,2005,3(3):179-181. 被引量:5
  • 2侯伯亨 顾新.VHDL硬件描述语言与数字逻辑电路设计[M].西安:西安电子科技大学出版社,1998..
  • 3[1]Gallager R G.Low-density parity-check codes[M].MA:MIT Press,1963.
  • 4[2]MacKay D J C,Neal R M.Near Shannon Limit Performance of Low-Density Parity-Check Codes[J].Electronic,Lett.,1996,32(18):1645-1646.
  • 5[3]Sae-Yong Chung,G David Forney Jr,Thomas J Richardson,et al.On the Design of Low-Density Parity-Check Codes within 0.0045dBof Shannon Limit[J].IEEE Communications Letters,2001,5(2):58-60.
  • 6[4]Futaki H,Ohtsuki T.Low-Density parity-check(LDPC) coded OFDM systems with M-PSK[C]// IEEE VTC2002,2002:1035-1039.
  • 7[7]MacKay D J C.Good Error-Correcting Codes based on very Sparse Matrices[J].IEEE Trans.Inform Theory,1999,45(5):399-431.
  • 8[8]Ungerboeck G Trellis.Codes Modulation with Redundant Signal State Sets Part 2:State of the Art[J].IEEE Communications Magazine,1987(2):12-21.
  • 9[9]Limpaphayom P,Kim A Winick.Power-and-Bandwidth-Efficient Communications Using LDPC Codes[J].IEEE Trans.On Communication,2004(3):350-354.
  • 10[10]Hagenauer J,Hoeher P.A vierbi algorithm with soft-decision outputs and its applications[C]// Proc IEEE GLOBECOM'89,1989,3:1680-1686.

共引文献10

同被引文献19

  • 1Gallager R G. Low density parity check codes[J]. IEEE Trans. Information Theory, 1962,8(1):21-28.
  • 2ZHANG T,Parhi K K. VLSI implementation oriented(3,k)-regular low-density parity-check codes[C]// IEEE Proc. of SIPS.[S.l.]:IEEE, 2001:25-36.
  • 3CHEN Y,Parhi K K. Overlapped message passing for quasi-cyclic low-density parity check codes[J]. IEEE Trans. Circuitsand Systems, 2004,51(6):1106-1113.
  • 4DAI Y M,YAN Z Y,CHEN N. Optimal overlapped message passing decoding of quasi-cyclic LDPC codes[J]. IEEE Trans.VLSI, 2008,16(5):565-578.
  • 5CHEN X,KANG J,LIN S,et al. Memory system optimization for FPGA-based implementation of quasi-cyclic LDPC codesdecoders[J]. IEEE Trans. Circuits and Systems, 2011,58(1):98-111.
  • 6Darabiha A,Carusone C,Kschischang F R. Block-interlaced LDPC decoders with reduced interconnect complexity[J]. IEEETrans. Circuits and SystemsII, 2008,55(1):74-78.
  • 7GB 20600-2006. Framing structure,channel coding and modulation for digital television terrestrial broadcastingsystem[S]. Beijing:[s.n.], 2006.
  • 8Gallager R. Low density parity check codes[J]. IRE Trans. on Inform. Theory, 1962,IT-8(1):21-28.
  • 9MacKay D J C,Neal R M. Near Shannon limit performance of low density parity check codes[J]. Electro. Lett., 1996,32(18):1645-1646.
  • 10WU Zijing,SU Kaixiong,GUO Liting. A modified Min Sum decoding algorithm based on LMMSE for LDPC codes[J]. AEUInternationalJournal of Electronics and Communications, 2014,68(10):994-999.

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