摘要
设计了一种应用于超高频射频识别（UHFRFID）阅读器的A∑Fractional-N频率综合器。该频率综合器采用开关电容阵列结构实现了调谐范围为750—950MHz的压控振荡器，使用电流模式逻辑（CML）结构D触发器实现了7—8双模预分频，频率精度设计为1．98kHz，电路基于UMC0．181xm2层多晶6层金属CMOS工艺实现，芯片面积为1700μm×1950μm。仿真结果表明系统建立时间小于1001xs。系统相位噪声的Matlab仿真结果为-115dBc／Hz@500kHz。测试结果显示电源电压1．8V时功耗15mA，总输出相位噪声为-111．45dBc／Hz@500kHz，测试的输出频率较好地符合预置输出频率。
A △ ∑. fraction-N frequency synthesizer for single chip UHF RFID （ultra high frequency radio frequency iden- tification） readers was designed and implemented. The design of the frequency synthesizer adopts a switch-capaci- tor array to achieve its multiple band voltage controlled oscillator and tuning range of 750 - 950MHz, and uses a current module logic （CML） D flip-flop to realize a dual 7 -8 pre-divider. The frequency accuracy of the frequen- cy synthesizer was designed for 1.98kHz. The simulation result showed the setup time of the system was less than 100μs, and the Matlab simulation showed the system phase noise was - 115dBc/Hz@ 500kHz. This synthesizer was fabricated in the UMC 0. 181xm double-poly six-metal CMOS process technology, with a die size of 1700μm x 19501xm. The experimental results showed that the chip dissipated a current of 15mA current under a supply volt- age of 1.8V, the total phase noise was -111.45dBc/Hz@ 500kHz, and the output frequency was coincident with the preset.
出处
《高技术通讯》
CAS
CSCD
北大核心
2012年第12期1286-1291,共6页
Chinese High Technology Letters
基金
863计划（2008AA04A102）资助项目.
