面向内容安全硬件加速的主从协同处理模型

Master-salve co-processing model for content security hardware accelerating

随着网络带宽超越摩尔定律的高速增长,基于通用处理器的软件算法无法满足高速网络的性能要求,设计利用专用硬件结构才能更大限度地提高性能,但硬件结构的使用不像软件算法只需调用函数接口那样简单。针对网络安全系统的性能瓶颈问题,设计实现了一个基于主从协同处理模型的内容安全硬件加速卡,该加速卡通过标准总线协议与主机通信,采用可编程逻辑器件实现特征匹配结构。该模型可减少网络安全系统使用硬件结构时的系统修改,并使两者协同工作,提高数据交换效率,优化系统整体性能。

With the rapid development of network speed exceeding Moore Law,the performance of software algorithms based on universal processor cannot match the need of high network speed.A special hardware architecture can improve the performance more efficiently while it is not as simply utilized as software application programming interface.For the performance bottleneck in network security system,a master-slave co-processing model for hardware pattern matching architecture is proposed.Based on the model,a content-based pattern matching accelerator card is designed and realized.The pattern match hardware architecture is implemented in the accelerator card on FPGA,working with PC server through standard bus protocol.The model reduces software development work when using the hardware card replacing software lib,and improves the data exchanging efficiency and the system performance through network security system.