期刊文献+

Increasing substrate resistance to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS 被引量:3

Increasing substrate resistance to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS
原文传递
导出
摘要 With the impact of the non-uniform turn-on phenomenon,the ESD robustness of high-voltage multifinger devices is limited.This paper describes the operational mechanism of a GG-nLDMOS device under ESD stress conditions and analyzes the reason that causes the non-uniform turn-on characteristics of a multi-finger GGnLDMOS device.By means of increasing substrate resistance,an optimized device structure is proposed to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS.This approach has been successfully verified in a 0.35 m 40 V BCD process.The TLP test results reveal that increasing the substrate resistance can effectively enhance the turn-on uniformity of the 40 V multi-finger GG-nLDMOS device and improve its ESD robustness. With the impact of the non-uniform turn-on phenomenon,the ESD robustness of high-voltage multifinger devices is limited.This paper describes the operational mechanism of a GG-nLDMOS device under ESD stress conditions and analyzes the reason that causes the non-uniform turn-on characteristics of a multi-finger GGnLDMOS device.By means of increasing substrate resistance,an optimized device structure is proposed to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS.This approach has been successfully verified in a 0.35 m 40 V BCD process.The TLP test results reveal that increasing the substrate resistance can effectively enhance the turn-on uniformity of the 40 V multi-finger GG-nLDMOS device and improve its ESD robustness.
出处 《Journal of Semiconductors》 EI CAS CSCD 2013年第1期49-52,共4页 半导体学报(英文版)
关键词 ESD multi-finger GGLDMOS turn-on uniformity ESD multi-finger GGLDMOS turn-on uniformity
  • 相关文献

参考文献8

  • 1Chun J, Nowak E, Manley M. Process and design for ESD robust- ness in deep submicron CMOS technology. IEEE International Reliability Physics Symposium, 1996:233.
  • 2Oh K H, Duvvury C, Banerjee K, et al. Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors. IEEE Trans Electron Devices, 2002, 49(12): 2171.
  • 3Chen T Y, Ker M D. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices. IEEE Trans Device Mater Reliab, 2001, 1(4): 190.
  • 4Russ C, Bock K, Rasras M, et al. Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing. Electrical Overstress/Electrostatic Dis- charge Symposium Proceedings, 1998:177.
  • 5Lee J H, Wu Y H, Tang C H, et al. A simple and useful layout scheme to achieve uniform current distribution for multi-finger silicided grounded-gate NMOS. IEEE International Reliability Physics Symposium, 2007:588.
  • 6Ker M D, Chen T Y. Substrate-triggered technique for on-chip ESD protection design in a 0.18 μm salicided CMOS process. IEEE Trans Electron Devices, 2003, 50(2): 1050.
  • 7Polgreen T L, Chatterjee A. Improving the ESD failure thresh- old of silicided n-MOS output transistors by ensuring uniform current flow. IEEE Trans Electron Devices, 1992, 39(2): 379.
  • 8Fujiwara S, Nakaya K, Hirano T, et al. Source engineering for ESD robust NLDMOS. Electrical Overstress/Electrostatic Dis- charge Symposium Proceedings, 2011:1.

同被引文献12

引证文献3

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部