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A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp 被引量：2

A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp
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摘要 The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs. The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
作者 潘红伟 刘斯扬 孙伟锋
机构地区 National ASIC System Engineering Research Center
出处 《Journal of Semiconductors》 EI CAS CSCD 2013年第1期53-57,共5页 半导体学报（英文版）
基金 Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059) the Program for New Century Excellent Talent in University (No.NCET-10-0331)
关键词 ESD protection ESD robustness SCR-LDMOS LATCH-UP holding voltage ESD protection ESD robustness SCR-LDMOS latch-up holding voltage
分类号 TN386.1 [电子电信—物理电子学]
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参考文献11

  • 1Vashchenko V A, Concannon A, Beekter M, et al. High hold- ing voltage cascaded LVTSCR structures for 5.5 V tolerant ESD protection clamps. IEEE Trans Device Mater Reliab, 2004, 4(2): 273.
  • 2Miao M, Dong S, Li M, et al. Trigger voltage walk-in effect of ESD protection device in HVCMOS. IEEE International Confer- ence on Solid-State and Integrated Circuit Technology, 2010.
  • 3Vashchenko V A, Concannon A, Beek M T, et al. Comparison of ESD protection capability of lateral BJT, SCR and bidirectional SCR for high-voltage BiCMOS circuits. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2002.
  • 4Keppens B, Mergens M P J, Cong S T, et al. ESD protec- tion solutions for high voltage technologies. Electrical Over- stress/Electrostatic Discharge Symposium, 2004.
  • 5Pendharkar S, Teggatz R, Devore J, et al. SCR-LDMOS-a novel LDMOS device with ESD robustness. International Sym- posium on Power Semiconductor Devices and ICs, 2000.
  • 6Liu Z, Liou J J, Vinson J. Novel silicon-controlled rectifier (SCR) for high-voltage electrostatic discharge (ESD) applications. IEEE Electron Device Lett, 2008, 29(7): 753.
  • 7Meneghesso G, Tazzoli A, Marino F A, et al. Development of a new high holding voltage SCR-based ESD protection structure. IEEE International Reliability Physics Symposium, 2008.
  • 8Chen W Y, Ker M D. Improving safe operating area ofnLDMOS array with embedded silicon controlled rectifier for ESD protec- tion in a 24-V BCD process. IEEE Trans Electron Devices, 2011, 58(9): 2944.
  • 9Ker M D, Lin K H. The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latch-free power-rail ESD clamp circuit for LCD driver ICs. IEEE J Solid- State Circuits, 2005, 40(8): 1751.
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同被引文献13

  • 1BART K, MERGENS M P J, TRINH C S, et al. ESD protection solutions for high voltage technologies[J]. Microelectronics Reliability, 2006, 46:677-688.
  • 2TAZZOLI A, MARINO F A, CORDONI M, et al. Holding voltage investigation of advanced SCR-based protection structures for CMOS technology[J]. Microelectronics Reliability, 2007, 47:1444-1449.
  • 3YANG Liu, WANG Yang, ZHOU Acheng, et al. Design, fabrication and test of novel LDMOS-SCR for improving holding voltage[J]. Solid-State Electronics, 2015, 103:122- 126.
  • 4SALCEDO A, LIOU J, LIU Zhi-wei, et al. Vinson TCAD methodology for design of SCR devices for electrostatic discharge (ESD) applications[J]. IEEE Transactions on Electron Devices, 2007, 54(4): 822-832.
  • 5GUIDO N, FRED K, JAN M L. Using an SCR as ESD protection without latch-up danger[J]. Microelectronics Reliability, 1997, 37(10/11): 1457-1460.
  • 6CHANG W J, KER M D. The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology[J]. IEEE Trans Device Mater Reliability, 2007, 7(2): 324-332.
  • 7VASHCHENKO V A, CONCANNON A, TER BEEK, et al. High holding voltage cascaded LVTSCR structures for 5.5 V tolerant ESD protection clamps[J]. IEEE Trans Device Mater Reliab, 2004, 4(2): 273-280.
  • 8MENEGHESSO Q TAZZOLI A, MAR1NO F A, et al. Development of a new high holding voltage SCR-based ESD protection stmcture[C]//IEEE International Reliability Physics Symposium. Phoenix, AZ, USA: IEEE, 2008.
  • 9LI Wang, RUI Ma, CHEN Zhang, et al. Sealable behavior modeling for SCR based ESD protection structures for circuit simulation[C]//IEEE International Symposium on Circuits and Systems (ISCAS). Melbourne, Australia: IEEE, 2014.
  • 10蒋苓利,张波,樊航,乔明,李肇基.ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR[J].Journal of Semiconductors,2011,32(9):34-37. 被引量：3

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Journal of Semiconductors
2013年 第1期

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