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Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS 被引量:2

Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS
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摘要 Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET (GGNMOS) was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse (TLP) measurements and Sentaurus technology computer aided design (TCAD) 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail. Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET (GGNMOS) was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse (TLP) measurements and Sentaurus technology computer aided design (TCAD) 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail.
出处 《Journal of Semiconductors》 EI CAS CSCD 2013年第2期41-45,共5页 半导体学报(英文版)
关键词 ESD channel length GGNMOS current spreading ESD channel length GGNMOS current spreading
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  • 1Salman A, Gauthier R, Stadler W, et al. NMOSFET ESD self- protection strategy and underlying failure mechanism in ad- vanced 0.13-/zm CMOS technology. IEEE Trans Device Mater Reliab, 2002, 12(1): 2.
  • 2Oh K H, Banerjeel K, Duvwg C, et al. Non-uniform conduction induced reverse channel length dependence of ESD reliability for silicided NMOS transistors. IEEE IEDM, 2002:341.
  • 3Pogany D, Johnsson D, Bychikhin S, et al. Measuring holdingvoltage related to homogeneous current flow in wide ESD pro- tection structures using multilevel TLP. IEEE Trans Electron De- vices, 2011, 58(2): 411.
  • 4Dong S, Du X, Han Y, et al. Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications. IEEE Electron Lett, 2008, 44(19): 1129.
  • 5Lee J H, Wu K M, Huang S C, et al. The dynamic current dis- tribution of a multi-fingered GGNMOS under high current stress and HBMESD events. IEEE Reliab Phys Symp Proc, 2006:629.
  • 6Chen T Y, Ker M D. Analysis on the dependence of layout para- meters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process. IEEE Trans Semicond Man- ufacturing, 2003, 16(3): 486.
  • 7Bock K, Russ C, Badenes G, et al. Influence of well profile and gate length on the ESD performance of a fully silicided 0.25/zm CMOS technology. IEEE Trans Components, Packaging, and Manufactory Technology-Part C, 1998, 21(4): 286.
  • 8Bock K, Keppens B, De Heyn V, et al. Influence of gate length on ESD-performance for deep submicron CMOS technology. EOS/ESD Symposium, 1999:95.
  • 9Sze S M. Physics of semiconductor devices. 3rd ed. New York: Wiley, 2007:257.
  • 10Chen X B, Zhang Q Z. Theory and design of transistors. 2nd ed. Beijing: Publishing House of Electronics Industry, 2008:132 (in Chinese).

同被引文献16

  • 1邱亮,张之圣.ESD的物理失效分析及放电路径的研究[J].电子测量技术,2007,30(3):6-9. 被引量:10
  • 2陈强,郭志蓉,周晶.在半导体器件中进行失效分析的方法:中国,101769876A[P].2010-07-07.
  • 3KER M D, CHEN S H, CHUANG C H. ESD failure mechanisms of analog I/O cells in O. 18-i.Lm CMOS technology [ J ]. IEEE Transactions and Materials Reliability, 2006, 6 (1): 102-111.
  • 4陈险峰,李明.暴露半导体衬底的方法和失效分析方法:中国,101996880A[P].2011-03-30.
  • 5CLAUDIO R A, BURGESS A, BRANCO C M, et al. Failure analysis of scratch damaged shot peened simulated components at high temperature [ J ]. Engineering Failure Analysis, 2009, 16 (4) : 1208 - 1220.
  • 6马忠良,贾新章.CMOS集成电路ESD研究[D].西安:西安电子科技大学,2008.
  • 7KER M D, WU T S. ESD protection for submicron CMOS IC's-A Tutorial [ J]. CCL Technical Journal, 1995, 42 (9): 10-24.
  • 8孙静,钱峰.对栅氧化层进行失效分析的方法:中国,101996911A[P].2011-03-30.
  • 9ALVAREZ D, ABOU-KHALIL M J, RUSS C, et al. Analysis of ESD failure mechanism in 65 nm bulk CMOS ESD NMOSFETs with ESD implant [ J ]. Microelectronics Reliability, 2006, 46 (9/10/11): 1597 - 1602.
  • 10NEVER J M, VOLDMAN S H. Failure analysis of shallow trench isolated ESD structures [ C ] //Proceedings of IEEE Electrical Overstress/Electrostatic Discharge Symposium. Phoenix, AZ, USA, 1995: 273 -288.

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