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A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS 被引量:1

A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS
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摘要 A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented. It features a selectable interpolation rate (2x/4x/8x) with a programmable interpolation filter. To improve the high-frequency performance, a "fast switching" technique that adds additional biasing to the current-switch is adopted. The datadependent clock loading effect is also minimized with an improved switch control by using a double latch. This DAC is implemented in 65 nm CMOS technology with an active area of 1.56 mm2. The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal, respectively. A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented. It features a selectable interpolation rate (2x/4x/8x) with a programmable interpolation filter. To improve the high-frequency performance, a "fast switching" technique that adds additional biasing to the current-switch is adopted. The datadependent clock loading effect is also minimized with an improved switch control by using a double latch. This DAC is implemented in 65 nm CMOS technology with an active area of 1.56 mm2. The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal, respectively.
出处 《Journal of Semiconductors》 EI CAS CSCD 2013年第2期78-85,共8页 半导体学报(英文版)
基金 Project supported by the National High Technology Research and Development Program of China(No.2009AA011605) the National Natural Science Foundation of China(No.61076027)
关键词 DAC high speed high resolution PROGRAMMABLE DAC high speed high resolution programmable
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参考文献10

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同被引文献8

  • 1Lin, Chi-Hung,Van Der Goes, Frank M. L.,Westra, Jan R.,Mulder, Jan,Lin, Yu,Arslan, Erol,Ayranci, Emre,Liu, Xiaodong,Bult, Klaas.A 12 bit 2.9 GS/s DAC with IM3 < 60 dBc beyond 1 GHz in 65 nm CMOS. IEEE Journal of Solid State Circuits . 2009
  • 2AD9765:12-bit 125-MS/s dual channel TxDAC. .
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  • 4Hyde, John,Humes, Todd,Diorio, Chris,Thomas, Mike,Figueroa, Miguel.A 300-MS/s 14-bit digital-to-analog converter in logic CMOS. IEEE Journal of Solid State Circuits . 2003
  • 5Lakshmikumar K R,Hadaway R A,Copeland M A.Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE Journal of Solid State Circuits . 1986
  • 6Chan, Kok Lim,Zhu, Jianyu,Galton, Ian.Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs. IEEE Journal of Solid State Circuits . 2008
  • 7Yonghua Cong,Geiger, R.L.A 1.5-V 14-bit 100-MS/s self-calibrated DAC. Solid-State Circuits, IEEE Journal of . 2003
  • 8徐震,李学清,刘嘉男,魏琦,骆丽,杨华中.A 14-bit 500-MS/s DAC with digital background calibration[J].Journal of Semiconductors,2014,35(3):152-157. 被引量:1

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