COMS电路的参数提取及模型建立

Parameter Extraction and Modelling of CMOS Circuit

静态时序分析是验证时序是否收敛的重要手段,但它需要准确的时序模型,尤其是全定制电路不能使用一般晶圆工厂提供的时序工艺库。这里介绍了使用synopsys公司的各种工具进行寄生参数的提取,瞬态分析和时序模型的建立,并以传输管为例,详细描述了建立查找表时序模型的流程。

Static timing analysis is an important method to verify the convergence of timing, hut it require accurate timg model, especially the full customed circuit can not use the common timing technology library provided by the foundary. Introduced extraction of parasitical parameters, transient analysis and building of timing models by using synopsys tools,and using transport transistors as an example,depicted flow of constituting timing models of looking - up table.