一种基于Ivds接口的时钟恢复电路实现

A LVDS port based realization of clock data recovery architecture

本文设计了一种基于时间过采样结构的时钟恢复方案,在EP2C20 FPGA平台基于LVDS信道实现了数据流编解码和收发接口相应功能,通过5倍速同频高速采样检测数据边沿,通过这种结构,能够彻底消除在信道传输过程中叠加的数据抖动,从而消除毛刺干扰,并在接收侧同步恢复出发送端同相时钟,保证对发送端的跟踪性能。

In this paper a LVDS port based clock data recovery architecture was designed and realized on the FPGA platform of EP2C20,using 5 times speed clock to sample the data transition edge ,with this architecture to recovery the origin same-phase clock and data of transmitter ,and the clock and data jitter tolerance can be enhanced ,so the pulse leap been eliminated, increased the tracking loop performance.