可重构的串行高级加密标准加解密电路设计

Reconfigurable serial AES encryption and decryption circuit design

为了进一步提高高级加密标准(AES)算法在现场可编程门阵列(FPGA)上的硬件资源使用效率,提出一种可支持密钥长度128/192/256位串行AES加解密电路的实现方案。该设计采用复合域变换实现字节乘法求逆,同时实现列混合与逆列混合的资源共享以及三种AES算法密钥扩展共享。该电路在Xilinx Virtex-Ⅴ系列的FPGA上实现,硬件资源消耗为1871 slice、4 RAM。结果表明,在最高工作频率173.904 MHz时,密钥长度128/192/256位AES加解密吞吐率分别可达2119/1780/1534 Mb.s-1。该设计吞吐率/硬件资源比值较高,且适用支持千兆以太网。

To improve the efficiency of hardware resources of the Advanced Encryption Standard （AES） algorithm on the Field Programmable Gate Array （FPGA）, an implementation method of serial AES circuit that could perform both encryption and decryption with 128/192/256 bit key options was proposed. The design computed byte multiplication inverse in composite field transform, integrated MixColumn and InvMixColumn circuits, and fused three kinds of key expansion algorithms at the same time. The design was implemented in Xilinx FPGA Virtex-V and the consumption of hardware resources was 1 871 slices, 4 block RAM. The results show that the throughput can be up to 2119/1780/1534 Mb · s ^-1 for 128/192/256 bit key length while the maximum frequency is 173. 904 MHz. The design achieves high throughput/hardware resource ratio and can be applied to the Gigabit Ethemet.