1024位CCD模拟延迟线的研制

Research and Development of 1024 Bit CCD Analog Delay Lines

本文介绍了我所研制的1024位CCD模拟延迟线的基本原理和结构设计,着重讨论了器件参数及提高器件参数的途径。

A 1024 bit CCD analog delay line has been fabricated.The fun- demental principle and configuration of the device are prescnied together with discussions on device parameters as well as approaches to performance improve-