可动态配置维特比译码器的设计与实现

Design and Implement of a Dynamic Configuration for Viterbi Decoder

新一代移动无线通信系统的高速发展已成为现代通信技术的研究热点.本文设计了一种多速率多调制方式的可动态配置译码深度的Viterbi译码器,根据系统不同的调制方式,自适应控制模块动态的配置系统参数,选择系统调制方式下的最佳译码深度.对比传统的Viterbi算法,对分支度量模块(BMU)、幸存路径存储模块(SMU)进行了优化,在Xilinx公司的SC4VSX35硬件平台上进行了FPGA测试验证,结果表明该设计完全满足自适应配置要求,硬件资源占用、译码延迟、系统功耗均得到了优化.

A new generation of mobile communication system has become the researching hotspot of mod- em communication techniques. In this paper, a Viterbi decoder which has several different running speed and different types of modulation mode was design, and its decoding depth can be configured dynamically. According to different modulation mode of the system, adaptive control module confignreed the best decoding depth dynamically. Comparing with the traditional Viterbi algorithm, the branch measure module （BMU） and survived path storage module （SMU） were improved. The design was implemented on a FPGA Development board of Xilinx. The results show that the design completely meets the adaptive configuration requirements. The hardware re- sources occupation, decoding delay and the power consumption of the system are all optimized.