45nm双大马士革Cu互连逆流电迁移双峰现象及改善

45 nm Dual Damascene Cu Interconnect Upstream Electromigration Bimodality and Its Improvement

集成电路中金属连线的逆流电迁移(EM)的双峰失效现象在45 nm双大马士革低k材料铜布线工艺中变得尤为突出,介绍了由于空洞存在于连接电路导致电迁移的早期失效,总结出两个早期失效的主要原理:分别是空洞形成在通孔以及浅槽与通孔的斜面,这是由于淀积扩散阻挡层和铜工艺在上述两个地方存在弱点,越薄的扩散阻挡层厚度对EM越不利。因为偏薄的扩散阻挡层不利于阻挡铜扩散,尤其在通孔的侧壁和边角斜面,这样在测试电迁移的高温大电流下,铜在通孔侧壁和边角斜面处易扩散而形成空洞,最终导致芯片失效。实验表明可以通过优化双大马士革结构通孔以及浅槽与通孔的斜面的长宽比(AR)减少消除这些弱点。介质层(ILD)的厚度,浅槽的深度以及通孔的关键尺寸可以作为调节AR的主要方法。

The bimodality of upstream electromigration （EM） failures of IC metal interconnection in the dual damascene structure of 45nm Cu process with low-k material become especially. Voids exist in connection circuit induced electromigration early failure is introduced. Two major early failure modes with voids forming in via and at the chamfer of via-trench transition area are proposed. It is attributed to the liner process weakness at the respective locations, thinner barrier is not good for EM. It＇ s due to thinner barrier can not protect Cu diffuse, especially on via and at the chamfer of via-trench. When EM test with hot current and high temperature, void is easy to exist on such areas. It can be reduced and eliminated with the optimized via and chamfer aspect ratio （AR） defined by the dual damascene profile. Inter layer dielectric （ILD） thickness, trench etch depth, via critical dimension （ CD）, chamfer of via- trench transition profile etc. can serve as the tuning factors for the upstream EM bimodality improvement.