频率2GHz的16核处理器二级缓存设计

Design of a 2 GHz L2 Cache for 16-core Processor

提出了针对多核处理器的2级缓存L2Cache设计方案,以高效地处理访存请求.采用优化的目录协议维护与1级缓存L1Cache的数据一致性,并结合片上目录来维护L2Cache之间及其与3级缓存L3Cache之间的一致性;在L2Cache设计中,提出了基于MESIA-F的Cache一致性协议,实现了最早返回取数数据的短流水线设计;采用相关链和远程链机制解决了监听应答导致的死锁问题;通过基于流水线的睡眠与唤醒技术降低了漏流功耗;通过细粒度门控时钟降低了其动态功耗.后端设计结果表明,经过优化设计的L2Cache达到了频率2GHz的设计目标,并已成功应用于某16核处理器芯片.

An L2 Cache design scheme was provided to process the memory access with high efficiency. L2 Cache manages data coherency with L1 Cache by the improved directory protocol, and manages date coher- ence with other L2 Caches and L3 Caches by cooperating with directory control unit. An MESIA-F Cache coherency protocol was implemented. The stage of pipeline is small, so load data can be returned to core in advance. The potential deadlock was resolved by two dependence list. The leakage power is decreased by sleeping the data array and just waking up them before used. The dynamic power is decreased by applying the fine gate clock. The result of backend design shows that the design frequency reaches 2 GHz. The design has been used in a 16-core processor chip successfully.