CSP多核处理器芯片的低功耗设计

Low Power Design of a Multi-Core Processor Chip

提出了3种高主频多核处理器CSP芯片的功耗优化技术,即电源域间隔关断技术、流量感知的动态频率调节技术和层次式门控时钟技术.结果表明,3种优化技术对降低芯片功耗的作用均非常有效,能够不同程度地降低芯片的总功耗.其中,电源域间隔关断技术能够解决静态漏流功耗,流量感知的动态频率调节技术和层次式门控时钟技术能够控制动态功耗.

In order to implement low power design of Cool Symmetry Processor （CSP） which is a high fre- quency multi-core processor chip, three techniques are proposed for power reduction based on CSP struc- ture, that is interval power gating, dynamic frequency scaling based on throughput and hierarchical clock gating. The results of experiment show the three low power techniques reduce CSP chip power effectively. The interval power gating solves leakage power, the dynamic frequency scaling based on throughput and hierarchical clock gating can control dynamic power.