基于DSP Builder的插值滤波器的设计及FPGA实现

Design of interpolation filter based on DSP Builder and FPGA implementation

在数字接收机中,通常需要对采样的数据进行一定倍数的插值。采用Altera公司的DSP Builder设计工具,在MATLAB/Simulink中建立相应的算法模型并仿真。通过引入回路硬件模块,将硬件平台接入由Simulink构建的仿真测试回路中进行软硬件协同仿真,最后可以直接生成FPGA的下载文件。该方法简化了设计流程,降低了开发成本和周期,具有广阔的应用前景。

In the digital receiver, it often requires multiples samples of data corresponding interpolation. In this paper, using the DSP Builder of Altera to create the appropriate models and simulation algorithms in MATl.AB/Simulink. By introducing hardware- in-the-loop （HIL） module, it will link into the simulation test circuit built by Simulink to earlQr out the hardware and software cosimulation. Finally, it directly generates download documents for FPGA. This method simplifies the design process and reduces development costs and cycles, and has wide application prospects.