组合逻辑多故障诊断

Multi-Fault Diagnosis for Combinational Logic Circuits

通过对布尔差分法的剖析 ,得到了组合电路单固定故障测试生成的简化方法。该方法不必进行异或运算 ,只须求解恒等式就能得到组合逻辑电路的测试矢量。多故障的测试码产生可以对高阶布尔差分经过变换 ,转化为一阶布尔差分来处理 ,从而极大地减少了多故障测试生成的计算工作量。

Based on the anal ysis o f Boolean functions,a simplified method that generates test vectors for single f ault in c ombinational circuits is presented in th is parer.In this method,test vectors for combinational logic circuits can be obt ained only by solving an identity and no exclusive OR operations are needed.Test vectors for multi-fault can be generate d by turning higher order Boolean differ ence to first order Boolean difference,w hich dramatically decreases the amount o f work in calculating test generation of multi faults.