摘要
本文讨论了在源输入的确定赋值数最小时组合电路的测试生成方法后,介绍了基于可满足性的测试向量压缩的整数线性规划(ILP)模型。利用ISCAS85基准电路仿真的结果说明了用此模型求解压缩测试向量非常有效。
The problem of test pattern generation for single stuck-at fault in combinational circuits is discussed. Under the additional constraint conditions, the number of specified primary input assignments is minimized. The proposed approach is based on the integer linear programming (ILP) formulation which is built on an existing Propositional Satisflability (SAT) model for the test pattern generation.The experiment results on benchmark circuits show the applicability of proposed test pattern minimization model.
出处
《电路与系统学报》
CSCD
2000年第2期67-70,共4页
Journal of Circuits and Systems
关键词
数字电路
整数线性规划
测试向量
组合电路
Digital circuits,Integer linear programming,Automatic test pattern generation