纳米级低开销SEU免疫型XC Domino动态门

Nano-Scale Cost Effective SEU Immune XC Domino Dynamic Gate

在纳米级工艺条件下,高速运算单元核心部件XC Domino动态门面临严重的软错误问题.本文提出一种适用SEU类软错误容错设计的免疫型XC Domino动态门,此免疫型动态门借鉴了锁存器单元稳定结构,对于动态门的输出端实施P-type扩散区隔离以完成SEU的防护.通过Spectre电路仿真,验证了SEU免疫型动态门能够实现对于高达2倍Vdd振幅电压脉冲干扰的SEU类软错误容错;另外,与传统XC Domino动态门容错设计方案相比,免疫型动态门能够降低13.64%的门延时,并能在减少47.37%面积开销的同时降低75.54%功耗开销.

This paper focuses on researching the SEU fault tolerance of nano--scale Cross Couple Domino dynamic gate which builds essential parts of high performance micro-- processor. A novel single event upset immune XC Domino dynamic gate based on stable structure is proposed. Through circuit simulation by Spectre, the novel method can fulfill the SEU fault tolerance over glitches of double Vdd magnitude. Compared with conventional fault tolerant XC Domino dynamic gate, the SEU immune XC Domino dynamic gate obtained apparent advantages consisted of 13. 64% reduction in gate delay, 47. 37% reduction in silicon area and 75. 54% reduction in circuit power.