期刊文献+

Parallel architecture and optimization for discrete-event simulation of spike neural networks 被引量:5

Parallel architecture and optimization for discrete-event simulation of spike neural networks
原文传递
导出
摘要 Spike neural networks are inspired by animal brains,and outperform traditional neural networks on complicated tasks.However,spike neural networks are usually used on a large scale,and they cannot be computed on commercial,off-the-shelf computers.A parallel architecture is proposed and developed for discrete-event simulations of spike neural networks.Furthermore,mechanisms for both parallelism degree estimation and dynamic load balance are emphasized with theoretical and computational analysis.Simulation results show the effectiveness of the proposed parallelized spike neural network system and its corresponding support components. Spike neural networks are inspired by animal brains, and outperform traditional neural networks on complicated tasks. How- ever, spike neural networks are usually used on a large scale, and they cannot be computed on commercial, off-the-shelf com- puters. A parallel architecture is proposed and developed for discrete-event simulations of spike neural networks. Furthermore, mechanisms for both parallelism degree estimation and dynamic load balance are emphasized with theoretical and computa- tional analysis. Simulation results show the effectiveness of the proposed parallelized spike neural network system and its cor- responding support components.
出处 《Science China(Technological Sciences)》 SCIE EI CAS 2013年第2期509-517,共9页 中国科学(技术科学英文版)
基金 supported by the National Natural Science Foundation of China (Grant Nos. 61003082,60921062,61005077)
关键词 神经网络系统 并行体系结构 离散事件仿真 优化 离散事件模拟 平衡机制 动态负载 仿真结果 spike neural network, discrete event simulation, intelligent parallelization framework
  • 相关文献

参考文献1

二级参考文献10

  • 1http://www.top500.org/lists/2010/11, Dec. 1, 2010.
  • 2Yang X, Yan X, Xing Z, Deng Y, Jiang J, Zhang Y. A 64-bit stream processor architecture for scientific applications. In Proc. ISCA 2007, San Diego, USA, June 9-13, 2007, pp.210- 219.
  • 3http://www.top500.org/lists/2009/11, Dec. 1, 2010.
  • 4Rountree B, Lowenthal D K. Bounding energy consumption in largescale MPI programs. In Proc. SC2007, Nevada, USA, Nov. 10-16, 2007, pp.1-9.
  • 5A Berl, E Gelenbe,-M Di Girolamo, G Giuliani, H De Meer, M Dang, K Pentikousis. Energy-efficient cloud computing. The Computer Journal, 2009, 53(7): 1045-1051.
  • 6http://www.greenSOO.org/lists/2010/11/top/list.php?from=1&to=100, Dec. 1, 2010.
  • 7Kirk D. NVIDIA CUDA software and GPU parallel computing architecture. In Proc. ISMM2007, Montreal, Canada, Oct. 21-22, 2007, pp.103-104.
  • 8http://software.intel.com/en-us/articles/intel-vt uneamplifier-xe/, Dec. 1, 2010.
  • 9http://www.totalviewtech.com/home/, Dec. 1, 2010.
  • 10http://www.nvidia.com/docs/10/43395/NV_DS_Tesla_M2050_M2070_Apr10_LowRes.pdf, Dec. 1, 2010.

共引文献18

同被引文献66

引证文献5

二级引证文献53

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部