基于时-空冗余的集成电路老化失效防护方法

Aging failure protection for integrated circuit based on spatio-temporal redundancy

集成电路工艺水平进入深亚微米时代后,电路老化效应已成为威胁电路可靠性的新挑战。对电路老化导致的电路失效防护问题进行研究,提出了一种基于时-空冗余技术的失效防护方法。该方法根据老化的行为特征,通过冗余的时序单元对数据路径进行加固,并采用多时钟技术控制时序单元的采样过程。当电路出现因老化导致的时序错误时,通过冗余时序单元的二次采样纠正电路错误信号;同时,统一调整电路的时钟相位,保证每条数据路径都满足时序要求,防止电路失效的发生。方法在ISCAS'89基准电路中进行了测试。实验数据表明:在冗余时钟相位差达到时钟周期的20%时,该方法可以有效的将电路的平均故障间隔时间(MTTF)提高1倍以上。

Because the technology of IC has entered to the level of deep sub-micrometer, the circuit aging has became new challenge to the reliability of circuit. Transistor aging could cause the gradually degradation of circuit performance, and eventually lead to the timing error. In this paper, a novel method based on time and flip-flop redundancy is proposed to protect circuit from the influence of transistor aging. This method uses dual modular redundancy of flip-flop and multi-clock controlled by the self-adaptive phrase scaling cell. Two flip-flops could mask timing error from aging by automatically picking the right sampling as the output signal and regulating clock phase of both two flip-flops when the error occurs. The method is tested in ISCAS＇89 reference circuit. The experimental results show that this method is effec- tive to aging error resilient with no impact on normal function. once time with a 20% phase difference of clock cycle. And it could improve the mean time-to-failure （MTTF） to