摘要
描述了基于浮点处理单元的投影变换的硬件实现。以提高速度为设计目标,采用Verilog语言进行设计和实现,使用ISE进行逻辑综合,并用SystemVerilog进行建模验证。结果表明,本设计极大地提高了图形处理的速度。
This paper describes the hardware implementation of projection which based on float-point processing unit. In order to improve the speed, the hardware is designed and implemented on Verilog language, ISE is used for logic synthesis ,and SystemVerilog is used for verification. The result shows that the speed is increased by this design.
出处
《电子技术应用》
北大核心
2013年第2期42-44,47,共4页
Application of Electronic Technique
关键词
图形流水线
硬件实现
逻辑综合
投影变换
graphics pipeline
hardware implementation
logic synthesis
projection
