快速中值滤波算法的改进及其FPGA实现

Implementation of the improved fast median filtering algorithm based on FPGA

针对传统中值滤波算法排序量大、速度慢且处理效果模糊的问题,在快速中值滤波算法的基础上,提出了一种加入阈值比较、且具有更高并行流水结构的改进算法,并在现场可编程门阵列(FPGA)硬件平台上实现了该算法。实验结果表明,改进的快速中值滤波算法不仅减少了比较的次数,还更好地保护了图像的细节,可满足图像预处理对实时性的要求。

The speed of classical median filtering algorithm is slow because of a lot of sorting and it blurs the image, this paper introduces an improved algorithm by adding threshold comparison to the fast median filtering algorithm, which has a parallel pipeline structure. The improved algorithm is implemented on the platform of field programmable gate array（FPGA）.The experimental results show that the improved fast median filtering algorithm not only has less times of comparison but also better quality, meet the requirements of the image pre-processing of real-time over the software version of the same algorithm.