高清视频的H．264／AVC帧内预测的ASIC实现

ASIC Implementation of H. 264/AVC Intra Prediction for High-definition Video

为提高H．264／AVC视频压缩标准中帧内预测的处理速度，满足高清视频的实时编码的要求，本文主要提出了一种基于可重构设计的双通路的模式交替的帧内预测器的ASIC实现方案。在用硬件描述语言（VerilongHDL）实现整个设计的基础上，运用编译仿真工具进行了功能仿真，实验表明，该帧内预测器处理完一个宏块需要720时钟周期，采用时钟频率为200MHz，吞吐量为853Mbit／s，能够满足1920×1080的实时编码要求。

In order to improve the processing speed of the intra predictor in H. 264/AVC video compression to meet the requirements of real-time HD encodings, a dual pathway for interleaved scheme ASIC implementation is proposed based on a reconfigurable architecture in this paper. With the implementation of the whole design by using Verilog hardware description language, the functional simulation is carried out by using VCS. Simulation results show that this intra predictor takes 720 cycles to processe one macroblock and the throughput reaches 853 Mbit/s at the operating frequency of 200 MHz. This rate can meet the requirements of 1 080 x 1 920 real-time coding.