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闪存循环位图的损耗均衡机制研究 被引量:3

Research on wear-leveling mechanism of circle bitmap for flash memory
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摘要 为了提高闪存的寿命,提出了闪存寿命的数学表达式,研究了闪存寿命和损耗均衡机制的关系。通过研究现有的均衡损耗机制,设计了一种新的闪存循环位图的损耗均衡机制。在传统的系统架构,加入循环位图从而得到一种新的系统架构。通过动态写入和静态回收两个阶段详细描述了该机制的基本工作流程和方法。最后通过性能分析,证实该机制能够显著提高闪存物理块的损耗均衡程度,因此具有一定的应用价值。 To improve the flash memory lifetime, the mathematical expression of the flash memory lifetime is presented. The relation ship between the flash memory lifetime and the wearqeveling mechanism is studied. By researching the existing wearleveling mechanisms, a new wearleveling mechanism based on the circle bitmap is designed. Based on the traditional system architec tures, a new system architecture which includes a circle bitmap is designed. Through the dynamic writing and the static recycling phases, the basic working processes and methods of the new mechanism are introduced. That the mechanism improves the effi ciency of the wearleveling level of the blocks by the performance analysis is found, so it could be applied to the practical applica tions.
出处 《计算机工程与设计》 CSCD 北大核心 2013年第2期523-528,共6页 Computer Engineering and Design
基金 国家863高技术研究发展计划基金项目(2009AA01A405)
关键词 闪存 闪存寿命 损耗均衡机制 循环位图 静态控制指针 动态控制指针 flash memory flash memory lifetime wear-leveling mechanism circle bitmap static control pointer dynamiccontrol pointer
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参考文献3

  • 1潘立阳,朱钧.Flash存储器技术与发展[J].微电子学,2002,32(1):1-6. 被引量:29
  • 2Alan R Olson,Denis J. Langlois Solid state drives data reliability and lifetime[EB/OL].http://www.csee.umbc.edu,2008.
  • 3张冬.大话存储2-存储系统架构与底层原理极限剖析[M]北京:清华大学出版社,201150-60.

二级参考文献19

  • 1[6]Lucero E M, Challa N, Feilds J. A 16k-bit smart 5V-only EEPROM with redundancy [J]. IEEE J Sol Sta Circ,1983;18(10): 539-544.
  • 2[7]Van Houdt J.HIMOS - a high efficiency flash EEPROM cell for embedded memory applications [J]. IEEE Trans Electron Device, 1993;40(12):2255.
  • 3[8]Lenzlinger M, Snow E H. Fowler-Nordheim tunneling in thermally grown SiO2 [J].J Appl Phys,1969; 40: 278.
  • 4[9]Hisamune Y S. A high capacitive coupling ration (HiCR) cell for 3 V only 64 Mbit and future flash memories [A]. IEEE IEDM [C]. 1993.1922.
  • 5[10]Ohnakado T. Novel electron injection method using band-to-band tunneling induced hot electron (BBHE) for flash memory with a p-channel cell [A]. IEDM [C].1995. 279.
  • 6[11]Iwata Y. A high-density NAND EEPROM with block-page programming for microcomputer applications [J]. IEEE J Sol Sta Circ,1990;25(4): 417-424.
  • 7[12]Ajika B. A 5V only 16M bit flash EEPROM cell with a simple stacked gate structure [A]. IEDM [C].1990.115.
  • 8[13]Kobayashi S. Memory array architecture and decoding scheme for 3V-only sector erasable DINOR flash memory [J]. IEEE J Sol Sta Circ, 1994; 29(4): 454-460.
  • 9[14]Kim K S. A novel dual string NOR (DuSNOR) memory cell technology scalable to the 256M bit and 1G bit flash memory [A]. IEDM [C].1995.263.
  • 10[15]Dimaria D J. Trap creation in silicon dioxide produced by hot electrons [J]. J Appl Phys, 1989; 65(6): 2342-2355.

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