摘要
针对DDR3系统互联中信号完整性和时序等问题,以某自研的自主可控计算设备为背景,详细描述了龙芯3A处理器和四片DDR3内存颗粒芯片互联的仿真分析和优化设计方案。分析了IBIS模型的结构和数据信息,介绍了一种快速验证IBIS模型准确性的方案。仿真分析了一种DDR3差分时钟电路共模噪声的控制方法。利用前仿真和后仿真,分析验证了多片DDR3内存颗粒芯片在Fly-By拓扑结构下的时序和信号质量。仿真结果达到了预期目标。
In order to solve the signal integrity and timing problems in the interconnection of DDR3 system, a systemlevel simu lation analysis and optimal design of the interconnection for a Loongson 3A CPU and four DDR3 SDRAM chips are described. First, the structure of IBIS （Input/Output Buffer Information Specification） model is analyzed, and a method for verifying the accuracy of IBIS model quickly is described. Then the DDR3 differential clock circuit is simulated and a method to control com mon noise of differential circuit is verified. Last, the FlyBy topology used on the interconnection of CPU and Multichips is sim ulated and both the timing and signal quality are analyzed. The simulation results achieved the expected goals.
出处
《计算机工程与设计》
CSCD
北大核心
2013年第2期616-622,共7页
Computer Engineering and Design
