一种低电压低静态电流LDO的电路设计

Circuit design of LDO with low voltage and low quiescent current

设计一种低电压低静态电流的线性差稳压器。传统结构的LDO具有独立的带隙基准电压源和误差放大器,在提出一种创新结构的LDO,把带隙基准电压源和误差放大器合二为一,因而实现了低静态电流消耗的目的。设计采用CSMC0.5μm双阱CMOS工艺进行仿真模拟,这种结构LDO在轻负载情况下静态电流仅为1.7μA,输出暂态电压最大变化为9 mV。

A new simple structure of low-dropout regulator （LDO） which consumes low quiescent current is presented in this paper. Compared with the traditional LDO structures adopting separate bandgap circuit and error amplifing circuit, the pro- posed structure integrated these two circuits together. Therefore, it＇s possible for this LDO dissipating much less quiescent cur- rent which would be almost one half current of traditional LDO for the same performance. The main drawback is that the output voltage limits to bandgap voltage however that is not a significant problem in modern low power application. The proposed LDO was simulated in CSMC 0.5 μm twin-well CMOS process. The presented LDO dissipates 1.？ μA current under light load condi- tion and achieves 9 mV maximum transient voltage variation.