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12位200MS/s交织A/D转换器设计 被引量：3

Design of a 12-Bit 200 MS/s Time-Interleaved A/D Converter
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摘要 介绍了一个面向3G/4GLTE通信及雷达等应用的12位200MS/s的高速低功耗A/D转换器(ADC)。采用交织运放共享技术,可节省功耗,同时减小不同通道之间的增益失配、失调失配和带宽失配,提高ADC的性能。为了提高ADC的高频性能并避免时钟采样偏差带来的两路通道失配问题,采用一个工作在200 MS/s采样频率的统一的采样保持电路。芯片采用HJTC0.18μm 1P6MCMOS的工艺制造,核心电路面积为1.6×4(mm2),电源电压2.0V。流片测试结果表明,在4.9MHz的输入频率下,无杂散动态范围(SFDR)为83.1dB,信号噪声失真比(SNDR)为59.6dB,模拟核心电流为120mA,FOM1和FOM2值仅为0.08pJ/step和1.25pJ/step。 A 12-bit 200-MS/s analog-to-digital converter for 4G communication and radar systems was presented.In this ADC,time-interleaved and op-amp sharing technology to reduce power consumption,and decrease gain-mismatch,offset-mismatch and bandwidth-mismatch effects as well.To improve high frequency performance and prevent time-skew problems,an SHA operating at 200 MHz was adopted,which contained a high gain and bandwidth opamp.Fabricated in 0.18 μm HJTC 1P6M CMOS process,the core circuit occupied a chip area of 1.6 mm×4 mm.Test results showed that the ADC had an SFDR of 83.1 dB and SNDR of 59.6 dB for an fin of 4.9 MHz,while the core-analog circuit only consumed 120 mA of current from 2.0 V supply.The FOM1 and FOM2 were as low as 0.08 pJ/step and 1.25 pJ/step.
作者 程华斌 魏琦 赵南 杨华中
机构地区 清华大学电子工程系电路与系统研究所
出处 《微电子学》 CAS CSCD 北大核心 2013年第1期5-9,共5页 Microelectronics
基金 国家科技重大专项(2010ZX03006-003-01) 中国博士后科学基金资助项目(20100480258)
关键词 模数转换器 交织 运放共享 数字校正 A/D converter Time-interleave Op-amp sharing Digital calibration
分类号 TN792 [电子电信—电路与系统]
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参考文献1

二级参考文献17

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同被引文献24

  • 1WEN X K, WANG R, YANG S Y, et al. A 30 mW 10 b 250 MS/s dual channel SHA-less pipeline ADC in 0. 18 m CMOS [C] //Proceedings of IEEE 55'h Inter- national Midwest Symposium on Circuits and Systems. Boise, ID, USA, 2012: 1004-1007.
  • 2NAM J W, JEON Y D, YUN S J, et al. A 12 bit 100 MS/s Pipelined ADC in 45 nm CMOS [C] //Pro- ceedings of International SoC Design Conference. Jeju, Korea, 2011: 405-407.
  • 3ZHAO X X, LI F, WU B. A SHA-less 12 bit 200 MS/s pipeline ADC [ C] f/Proceedings of IEEE International Conference on Anti-Counterfeiting, Security and Identifi- cation. Xiamen, China, 2011: 161-164.
  • 4WANG K, FAN C J, ZHOU J J, et al. A 14 bit 100 MS/s CMOS pipelined ADC with 11.3 ENOB [J]. Journal of Semiconductors, 2013, 34 (8): 085015-1- 085015-5.
  • 5LIECHTI T, TAJALLI A, AKGUN O C, et al. A 1.8 V 12 bit 230 MS/s pipeline ADC in 0. 18 im CMOS technology [ C] // Proceedings of IEEE Asia Pacific Conference on Circuits and System. Macao, China, 2008: 21-24.
  • 6宋静慧.一种双通道8-bit200Msample/s时间交织流水线ADC的研究与设计[D].西安:西安电子科技大学,2012.
  • 7Nieminen T,Halonen K. An 1.2 V 440-Msample/s 0.13-pan CMOSPipelinedd Analog-to-Digital Converter with 5 bit - 8 bit Mode Selection [ R].
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  • 9谭瑁.3-3伏100兆采样频率10比特流水线结构模数转换器的设计和低功耗实现[D].复旦大学,2006.
  • 10Walden R H. Performance Trends for Analog-to-Digital Converters [J]. IEEE Commun Mag,1999,37(2) :86-101.

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微电子学
2013年 第1期

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